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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4021B MSI 8-bit static shift register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 8-bit static shift register DESCRIPTION The HEF4021B is an 8-bit static shift register (parallel-to-serial converter) with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH parallel load input (PL), eight asynchronous parallel data inputs (P0 to P7) and buffered parallel outputs from the last three stages (05 to O7). HEF4021B MSI Each register stage is a D-type master-slave flip-flop with a set direct/clear direct input. Information on P0 to P7 is asynchronously loaded into the register while PL is HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first register position and all the data in the register is shifted one position to the right on the LOW to HIGH transition of CP. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Fig.1 Functional diagram. HEF4021BP(N): HEF4021BD(F): HEF4021BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Fig.2 Pinning diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications PINNING PL P0 to P7 DS CP O5 to O7 parallel load input parallel data inputs serial data input clock input (LOW to HIGH edge-triggered) buffered parallel outputs from the last three stages January 1995 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 3 Product specification Fig.3 Logic diagram. Philips Semiconductors 8-bit static shift register HEF4021B MSI Philips Semiconductors Product specification 8-bit static shift register FUNCTION TABLES Serial operation INPUTS n 1 2 3 6 7 8 CP DS D1 D2 D3 X X X X PL L L L L L L L O5 X X X D1 D2 D3 OUTPUTS O6 X X X X D1 D2 no change O7 X X X X X D1 Notes n CP X HEF4021B MSI Parallel operation INPUTS DS X PL H O5 P5 OUTPUTS O6 P6 O7 P7 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition = negative-going transition Dn = either HIGH or LOW n = number of clock pulse transitions AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP On HIGH to LOW 5 10 15 5 LOW to HIGH PL On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW LOW to HIGH 10 15 5 10 15 5 10 15 tTLH tTHL tPLH tPHL tPLH tPHL 125 55 40 115 50 40 120 55 40 105 50 40 60 30 20 60 30 20 250 110 80 230 100 80 240 110 80 210 100 80 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 98 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 88 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 93 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 78 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA January 1995 4 Philips Semiconductors Product specification 8-bit static shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Set-up time DS CP 5 10 15 5 Pn PL Hold times DS CP 10 15 5 10 15 5 Pn PL Minimum clock pulse width; LOW Minimum PL pulse width; HIGH Recovery time for PL Maximum clock pulse frequency 10 15 5 10 15 5 10 15 5 10 15 5 10 15 fmax tRPL tWPLH tWCPL thold thold tsu tsu SYMBOL MIN. 25 25 15 50 30 20 40 20 15 15 15 15 70 30 24 70 30 24 50 40 35 6 15 20 TYP. -15 -10 -5 25 10 5 20 10 8 -10 0 0 35 15 12 35 15 12 10 5 5 13 30 40 MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz HEF4021B MSI see also waveforms Figs 4 and 5 VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 900 fi + (foCL) x VDD2 4 300 fi + (foCL) x VDD2 12 000 fi + (foCL) x VDD 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) January 1995 5 Philips Semiconductors Product specification 8-bit static shift register HEF4021B MSI Fig.4 Waveforms showing minimum clock pulse width, set-up time and hold time for CP and DS. Fig.5 Waveforms showing minimum PL pulse width, recovery time for PL, and set-up and hold times for Pn to PL. Set-up and hold times are shown as positive values but may be specified as negative values. January 1995 6 |
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